Intel lists five challenges for IC scaling
Mark LaPedus (02/09/2009 9:26 H EST)
SAN FRANCISCO -- Chip scaling will continue for the next several years, but
there are several challenges that face IC makers.
At the International Solid-State Circuits Conference (ISSCC) here, Mark Bohr,
Intel senior fellow and director of process architecture and integration at
Intel Corp. (Santa Clara, Calif.), outlined the challenges and potential
solutions. Bohr listed five major stumbling blocks--or challenges--for the
32-nm node and beyond:
1. Patterning or lithography
Problem: Wavelength has been scaling at a slower rate than the IC feature
size.
Current solutions: ''Resolution-enhancement techniques, such as
optical-proximity correction, phase-shift masks, and immersion lithography,
have been introduced to bring us to the 32-nm generation. But even with these
enhancements, layout restrictions, such as unidirectional features, gridded
layout and restricted line plus space combinations, have had to be gradually
adopted.''
Future solutions: ''Double-patterning techniques and computational
lithography are options being investigated to continue scaling to 22-nm and
possibly 16-nm generations before extreme ultraviolet (EUV) lithography could
be ready to provide a significant wavelength-reduction and resolution
enhancement.''
2. Transistor options
Problem: Classical scaling ended in the early 2000s due to gate oxide
leakage.
Current solutions: ''Strained silicon, high-k dielectrics and metal gates
have been significant innovations that have allowed MOSFET density,
performance and energy efficiency to show continued improvements past when
traditional scaling techniques ran out of steam.''
Future solutions: ''Substrate engineering makes use of wafers to improve
p-channel mobility, but may not offer any advantage for n-channel devices.
Multi-gate transistors such as FinFET, Tri-Gate and Gate-All-Around devices
offer improved electrostatics and steeper sub-threshold slopes, but may
suffer from higher parasitic capacitance and parasitic resistance.
''III-IV channel materials such as InSb, InGaAs and InAs are showing promise
for providing high switching speed at low operating voltage due to increased
carrier mobility, but challenges remain before a practical CMOS solution will
be ready.
3. Interconnect options
Problem: New solutions are required to slow resistivity and other problems.
Current solutions: Today's processes use copper interconnects, low-k and
other technologies to enable interconnect scaling at a rate of 0.7x per every
generation.
Future solutions: ''3-D chip stacking combined with through-silicon-vias
provides a high density of chip-to-chip interconnects. The downside of 3-D
chip stacking in this manner include the added process costs of (TSVs), the
silicon area lost on the chip that has vias cut through it, and the
challenges of delivering power and removing heat from the stack.
''Optical interconnects can address this bandwidth bottleneck if technologies
can be developed that cost effectively integrate photonics with silicon
logic. Using optical interconnects for on-chip signaling may be further off
in the future due to the difficulties with scaling optical transceivers and
interconnects to the dimensions required.''
4. Embedded memory
Problem: High-density memory beyond SRAM is needed in today's devices.
Current solution: Traditional 6T SRAM cells are used in processors and other
products.
Future solutions: ''In additional to traditional DRAM, eDRAM and flash-memory
options, floating body cell, phase-change memory and seek-and-scan probe
memory options all provide greater bit density than what 6T SRAM cells can
provide. But integrating a novel memory process together with a logic process
on a single wafer without compromising one or the other could be difficult.''
5. System integration
Problem: It is not sufficient to take smaller transistors as they become
available to simply make more complex versions of the same system components.
Current solutions: ''The new era of microprocessor scaling makes greater use
of energy efficiency, power management, parallelism, adaptive circuits and
SoC features to provide products that are many-core, multi-core and
multi-function.''
Future solutions: ''As we ponder the best paths to take in doing higher level
integration in the electronics world, we may consider examples provided by
nature (such as the human brain).
URL: http://www.eetimes.com/showArticle.jhtml?articleID=213402033
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