TSMC tips litho roadmap, backs maskless
Mark LaPedus (02/27/2009 11:45 H EST)
SAN JOSE, Calif. -- At the SPIE Advanced Lithography conference here, Taiwan
Semiconductor Manufacturing Co. Ltd. (TSMC) disclosed its lithography roadmap
and said it is still backing maskless technology.
Silicon foundry giant TSMC (Hsinchu) is ramping up its 40-nm logic process,
with plans to ship its new and previously-announced 28-nm technology in 2010.
Both the 40- and 28-nm processes will use 193-nm immersion lithography, said
Burn Lin, senior director of the micropatterning division at TSMC.
The real question at TSMC is the 22-nm node and beyond. For 22-nm, the
company is evaluating double-patterning, EUV and maskless. IBM Corp. and
others are pushing computational lithography for 22-nm, but Lin calls that
scheme a resolution enhancement technique (RET)--and not a next-generation
lithography (NGL) technology.
Considered the innovator behind immersion, Lin said that 193-nm ''wet''
technology can be extended to the 15-nm node (22-nm half-pitch logic), thanks
in part to double patterning.
Like many chip makers, TSMC may have to resort to double patterning; the
so-called NGL technologies are not ready. The trouble with double patterning
is that it is ''too expensive,'' Lin said.
If the other NGLs are late--and there is no choice in the matter--Lin said he
preferred a double-patterning scheme called litho-litho-etch (LLE), ''because
of cost.''
In doubling patterning, an IC maker is essentially doubling the process
steps, thereby boosting production costs. LLE may be cheaper than the rival
litho-etch-litho-etch (LELE) method, but LLE uses newfangled processes that
are somewhat unproven. LLE uses two lithography exposures and two resist
layers to create smaller IC features. In comparison, LELE uses two
lithography exposures and hard-mask etches to create smaller features.
A third method is called spacer or self-aligned double patterning. ''Spacer
is a double patterning technique that uses deposition, anisotropic
(directional) etching and trimming to produce smaller features on chips,''
according to ASML Holding NV.
Beyond doubling-patterning, there are a range of choices. Some are pushing
extreme ultraviolet (EUV), which uses 13.5-nm wavelength technology. As
reported, EUV lithography has been dogged by delays due to the lack of
sources, resists and masks. EUV is now being targeted for the 16-nm node.
EUV is 'too expensive,'' he said. The prices for EUV ''are difficult to pin
down.''
TSMC has yet to order an EUV tool. The company's main tool supplier--ASML
Holding NV--is currently selling a ''pre-production'' EUV tool, which will
ship next year. EUV tool costs are estimated to be about $90 million.
Like EUV, Lin is not a big fan of nano-imprint lithography. There are some
defect concerns about 1x masks and the templete process in IC production, he
said.
As in previous years, Lin said his ''preferred'' NGL is maskless technology,
which eliminates the photomask in the IC flow. At 22-nm, TSMC would like to
put maskless in mass production--in all of its fabs. The foundry giant itself
has invested in Mapper Lithography NV, a developer of maskless tools.
Mapper is slated to deliver a ''pre-alpha'' tool to TSMC by the second half
of the year, Lin said, adding that he is also watching the other maskless
players, such as IMS, KLA-Tencor, TEL/Multibeam and others.
The goal for maskless is to have a machine that sells for $5 million euros
($6.3 million) and produces 10 wafers an hour, he said.
Maskless is a lower-cost technology, but it has been under-funded and is not
mature. It's unclear if maskless will pan out, as the clock is ticking on the
technology. Vendors have been working on maskless for years. 2009 or 2010
''will be very critical for multi-beam e-beam'' technology, he added.
At SPIE, Advantest, IMS, KLA-Tencor, Mapper and Multibeam presented papers on
maskless or direct-write e-beam. KLA-Tencor Corp. disclosed its maskless
technology. Tokyo Electron Ltd. (TEL) plans to sell a maskless tool based on
Multbeam's technology.
Meanwhile, the eBeam Initiative, a multi-company effort dedicated to the
advancement of e-beam direct-write technology for semiconductor prototyping
and low-volume manufacturing, launched at the SPIE Advanced Lithography
conference.
The effort initially 20 companies from across the chip spectrum, including
EDA vendors, ASIC suppliers, makers of e-beam tools, photomask suppliers and
others. The group is lead by Direct2Silicon Inc. (D2S) and guided by a formal
steering committee that includes Advantest, CEA/Leti, e-Shuttle, Fujitsu
Microelectronics and Vistec.
Meanwhile, TSMC's vendor, Mapper, is also on the move. Late last year, Mapper
Lithography and CEA-Leti signed an agreement under which Mapper will ship its
300-mm electron-beam lithography platform to CEA-Leti in Grenoble.
The machine will be used for the so-called Imagine program. That effort will
cover a range of topics, including tool assessment, patterning and process
integration, data handling and cost of ownership studies.
In that program, IC companies will assess Mapper's technology for maskless
lithography in IC manufacturing. CEA-Leti and Mapper are currently in the
process of selecting semiconductor companies to join the program.
In R&D for several years, Mapper's e-beam maskless lithography tool is said
to use over 10,000 electron beams working in parallel to directly write
circuit patterns on a wafer, eliminating the need for the costly photomasks
used in current lithography machines.
Also in 2008, a new European program was hatched that will push the insertion
of maskless lithography for IC manufacturing at the 32-nm ''half-pitch'' node
in 2009.
The program is called Magic--or Maskless Lithography for IC manufacturing.
The group consists of two developers of maskless lithography tools: Mapper
Lithography of the Netherlands and IMS Nanofabrication AG of Austria. Magic
also consists of STMicroelectronics, CEA-Leti, Synopsys, Qimonda, KLA-Tencor,
Fraunhofer and others.
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=215400024
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