IBM Fellow: Moore's Law defunct
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A new twist on the annual design contest this year was a clock network
synthesis task. Twenty-seven teams (16 from the U.S.) entered, but only nine
survived.
"Research in EDA tools for clock synthesis is not as popular as other areas
such as placement or routing," said Phillip Restle, a research staff member
at IBM's Watson Research Center. "However, clock design automation is
actually much more difficult."
The task involved distributing a 2-GHz clock across a chip with picosecond
precision. IBM evaluated the submissions using seven benchmarks derived from
its most recent 45-nanometer designs. It verified results with electrical
circuit simulations using open-source tools and the Predictive Technology
Model created at Arizona State University.
Of the three winning entries, one came from the U.S.: "Contango", written by
Dongjin Lee, a graduate student working in the lab of Professor Igor Markov
at the University of Michigan.
"The contest was based on Spice simulation, and we found that even the
state-of-the-art analytical models were not accurate enough," said Markov.
"We had to put Spice inside our optimization flow."
The two other winning teams were National Taiwan University and National
Chiao-Tung University.
"This contest is a first step towards capturing concerns of industrial clock
synthesis, targeting rough estimates for real clock skew using Spice
simulations subject to power and slew constraints," said Rupesh Shelar, a
senior component design engineer at Intel Corp.
Prashant Saxena, the conference program chair and principal engineer at
Synopsys, said the new clock synthesis contest should spur new research into
areas neglected using more conservative clocking methodologies. The result,
Saxena said, will be better algorithms and more highly automated clocking
flows.
http://tinyurl.com/d55vwj
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