一樣, 也是請有空的人盡可能出席
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Title: The Evolution of Interconnect Management in Physical Synthesis
Speaker: Dr. Prashant Saxena, Synopsys Inc.
Time: 2:20-3:10 pm, April 27, 2009 (Monday)
Place: MD-231, NTUEE (明達館 231室)
Abstract:
With the worsening of interconnects due to scaling, the reliance
of the original physical synthesis paradigm on merely some
placement of the cells in order to predict net delays no longer
suffices. Practitioners have augmented this paradigm over the
years with increasingly sophisticated net models in an effort to
improve the accuracy of the interconnect delay predictions. In
this paper, we will review these advances and motivate their
natural evolution towards “guaranteed” net delays by describing
a new scheme known as “persistence”. Although a naive
implementation of persistence can result in unroutable circuits,
we will describe how persistence can be applied intelligently in
an industrial flow to improve the circuit optimization without
impacting its congestion.
Biography:
Prashant Saxena received the B.E. (Hons.) degree in electrical and
electronic engineering and the M.Sc. (Tech.) degree in computer
science from the Birla Institute of Technology and Science, Pilani,
India in 1991, and the Ph.D. degree in computer science from the
University of Illinois, Urbana-Champaign, in 1998.
He then spent the next decade pursuing VLSI CAD research at Intel
(Strategic CAD Labs, 1998-2004) and Synopsys (Advanced Technology
Group, 2005-2008). He currently serves as a Principal Engineer at
Synopsys, and is located in Hillsboro, OR, USA. He co-developed the
layout methodology for domino logic synthesis used on the 180 nm
Pentium? 4 design, and pioneered the noise convergence methodology
for the standard cell based portions of the 90 nm Pentium? 4 design.
Recently, he led the methodology development for and tapeout of an
asynchronous chip that yielded significant power benefits over its
commercially marketed synchronous counterpart. He has authored or
co-authored one book ("Routing Congestion in VLSI Circuits:
Estimation and Optimization", published by Springer 2007),
several book chapters, numerous papers in leading journals and
conferences, and the specification for the Virtual Socket
Interface Alliance (VSIA) signal integrity standard. His current
research interests are in physical synthesis and layout, logic
synthesis, signal integrity, process scaling issues, and
asynchronous circuit design.
Dr. Saxena has served on the organizing committee for the ACM
International Symposium on Physical Design (ISPD) since 2006,
where he recently chaired the technical program committee,
and will serve as General Chair for 2010. He has served on the
technical program committees for several IEEE and ACM conferences
(such as DAC, ISCAS, and ISPD), as well as on several National
Science Foundation (NSF) panels and ITRS and SRC task forces.
He was an invited speaker or panelist at several conferences,
and presented a tutorial at DATE'05. He was awarded the Intel
Architecture Group Trailblazer Award in 2000 and a Best Paper
Award at Intel's internal technical conference in 2003, besides
being nominated for a Best Paper Award at ISPD'05.
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