推 supermark:看成我是台積的主管... *surprise* XD 09/03 17:36
→ yuko703:XDDDDDDDDDDDDD 09/04 01:22
→ peterpong:我好像蠻適合的喔~~ 哈!! 09/17 09:16
是我台積的主管請我幫忙徵個人
如果有人有興趣的話~
就........
先跟我說好了.....XDDDDDDD
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Key Areas of Responsibility
1. Develop automatic Library/IP design flow
2. Deliver innovative automatic solutions for reduce Library/IP
development cycle time
Key Experience:
1. Above Master degree in Electrical/Electronics/Computer Engineering or
Computer Science.
2. Digital, analog, mixed-signal, RF, or memory design & EDA-flow (sch,
sim, rcx,etc).
3. Familiar with various programming language, i.e., C/C++, Perl, TCL,
Python etc.
4. Critical design methodology for advanced process below n40.
5. PDK, MEMs, spice-modeling, numerical-analysis is a plus.
Personal Attributes:
1. Open communication
2. Aggressive
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※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 140.112.48.67