[找人] Marvell - Senior ASIC design engineer

[keee (￾ N )]

MSEE with 5+ years of experience/PhD with working knowledge in following areas
preferred:

- Good understanding of DSP and communication building blocks
- Bluetooth, or other wireless baseband design/implementation experience
- Hand on lab experience to bringing up silicon sample
- Micro-architecture specification and verilog RTL coding
- Familiar with ASIC implementation flow: synthesis(DC), DFT, timing
  closure(PT-SI), and formal verification
- Verification test bench development
- Excellent communication skills


Experience in following areas a plus:

- Matlab, C/C++, Perl, shell script, or TCL.
- System Verilog/VMM
- Interfacing with physical designer for floor planning/power optimization/
  CTS/post layout timing closure.
- Mix signal and low power design.
- Complete product cycle experience from specification to production


Please send your resume to [e-mail]

P.S. 還蠻急的.. 請有興趣的人將resume寄到上面信箱!

--
※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 70.231.247.34
※ 編輯: keee            來自: 70.231.247.34        (06/21 14:48)
推 TripleC:貴公司最近狂找人, 是有什麼大project嗎?
推 ccchen:你們組要招人呀？
→ ccchen:m 公司這兩個月是星期一進多少人，星期五就走多少人，哈