[問題] verilog的問題

[whisp1222 ()]

module f2

integer file1, file2;
initial begin
                file1 = $fopen("file1");
                file2 = $fopen("file2");
                        $display("The number used for file 1 is %0d", file1);
                        $display("The number used for file 2 is %0d", file2);
                        $fdisplay(file1, "Hello File 1");
                        $fdisplay(file2, "Hello File 2");
                        $fdisplay(file1 file2, "Hello both files");
                        $fdisplay(file1 file2 | 1, "Hello files and screen");
                        $fdisplay(file1, "Good Bye File 1");
                        $fdisplay(file2, "Good Bye File 2");
                        $fclose(file1);
                        $fclose(file2);
        end
endmodule

想請問file id的問題
1是保留給screen 及 log file使用
file1的id是2
file2的id為何是4(因為我以為是3 還是id是亂跳的)

程式來源
http://www.netlibrary.com/Reader/
Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog
點view the book後
在這本電子書的p52頁

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◆ From: 163.26.236.76
※ 編輯: whisp1222       來自: 163.26.236.76        (04/10 19:01)
→ pheonix:$fopen沒有給mode會return multi-channel
→ pheonix:descriptor