[問題] verilog基本簡單的updown counter

[nichaellin (章魚)]

module Counter(clk,rst,slect,out);
input  [1:0]slect;
input  clk,rst;
output [9:0]out;
reg    [9:0]out;

always@(slect)
begin
    if(slect==2'd0)
        always@(posedge clk)
        begin
            if(rst)
            begin
                out=10'd0;
        end
            else if(out==10'd1023)
            begin
                out=10'd0;
        end
            else
            begin
                out=out+1'd1;
            end
        end
    if(slect==2'd1)
         always@(posedge clk)
         begin
             if(rst)
             begin
                 out=10'd1023;
         end
             else if(out==10'd0)
             begin
                 out=10'd1023;
         end
             else
             begin
                 out=out-1'd1;
             end
         end
    if(slect==2'd3)
         always@(posedge clk)
         begin
             if(rst)
             begin
                 out<=10'd0;
             end
             else if(out!=10'd1023)
                 out<=out+1'd1;
             end
             else(out!=10'd0)
                 out<=out-1'd1;
             end
         end
     end
     end module

條件我假設是可以讓他
1.往上數到1023
2.往下數到0
3.0~1023~0這樣數

可是compile不過

我是新手一直苦無解答QQ

不知道有沒有人能幫幫我

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→ nichaellin:我把end module改成endmodule
→ nichaellin:就可以了耶XD
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→ flarehunter:always裡面放always應該是不行的吧