1. BS/MS or EE/CS degree w/minimum 4~6 years of ASIC design experience or backend design flow/methodology
2. Familiar timing driving APR, CTS (clock tree synthesis), physical verification, DSM (deep-sub-micron) effect, layout, and back-end design flow/methodology
3. Can work independently and travel to US occasionally.
4. English communication skills are essential
5. 詳細資訊請上www.broadcom.com 或 上104找新加坡商博通亞洲股份有限公司
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