作者joey196t ( )
看板TFSHS65th316
標題[作業]verilog
時間Sat Apr 28 03:00:58 2007
有沒有高手會的啊 這個function主要在幹麻
IN 跟 OUT的關係是啥
module problem5_17(IN,OUT);
input [3:0]IN;
output [3:0]OUT;
reg [3:0]OUT;
always @(IN)
if (IN == 4'b0101) OUT = 4'b0001;
else if (IN == 4'b0110) OUT = 4'b0010;
else if (IN == 4'b0111) OUT = 4'b0011;
else if (IN == 4'b1001) OUT = 4'b0010;
else if (IN == 4'b1010) OUT = 4'b0100;
else if (IN == 4'b1011) OUT = 4'b0110;
else if (IN == 4'b1101) OUT = 4'b0011;
else if (IN == 4'b1110) OUT = 4'b0110;
else if (IN == 4'b1111) OUT = 4'b1001;
else OUT = 4'b0000;
endmodule
--
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→ joey196t:out = (in /4 的商+餘) ，請問這CODE的功能怎樣? 04/29 00:06
→ joey196t:幹...打錯 是乘不是加 04/29 00:08
推 amds:亂入 04/30 20:29
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推 philex:應該是沒錯吧 05/02 02:05
推 smove:樓上是...? 05/02 02:48
推 biggestbee:small love 05/02 12:24
推 ordinary07: 沒圖沒真相 05/02 12:33
推 joey196t:樓上想推的太老梗了 05/02 18:40