推 GN5566:問熟弟 他期末考75分 01/19 19:48
→ armstrong6v:我怎麼感覺你寫出來好像也會被當..? 好像只是幫你調 01/20 12:46
→ armstrong6v:分數的= = 就當我亂猜吧... 01/20 12:46
→ End1essRain:六十分過了! 好爽 陳振豐人真好 01/20 13:14
推 armstrong6v:恭喜 01/20 13:57
3. (a).Design a circuit that counts 16 clock cycles and produces a control signal , ctrl,
that is 1 during every sixth and tenth cycle
(b).Develop aVerilog model of the circuit from (a).
4.Develop a Verilog model for a pipeline circuit computes the average of corresponding values in four stresms of input values a, b, c and d.
The inputs and output are all signed fixed-point numbers indexed from 6 down
to -9.
有誰會阿 寫不出來就被盪了 拜託救我!!!
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