Computer Architecture
Homework #5 (Due 5/15, 5/22 )
(1) Cache Simulator (Due 5/22)
In this homework, you are asked to design a cache simulator. This simulator
should accept an address trace and a set of cache configuration as parameters
and report the cache miss ratio. The input format is specified below:
Input: address trace, cache size, cache block size, associativity
Example: cache trace1.dat 8192 32 2
cache: the executable file name for your simulator
trace1.data: file name of an address trace. An address trace is stored in
byte address format; that is, word 0 in memory is 0x00000000, word 1 is
0x00000004, word 2 is 0x00000008, etc. Cache size is 8192 bytes and the
cache block size is 32 bytes. It is a two-way set associative cache.
Note:
1.Please use C or C++ to implement the simulator if possible.
If you need to use other programming language, be sure to tell the TA
how to execute your simulator.
2. Assume LRU replacement policy.
3. Assume all memory references are reads.
4. Submission rule:
Email the TA your executable, source code and a readme file describing how
to run your simulator.
(2) Computer Architecture A Quantitative Approach 2Ed H&P 5.8
(3) Computer Architecture A Quantitative Approach 2Ed H&P 5.10
Note: Please email problem 1 to jenwei@cmlab.csie.ntu.edu.tw
. Put “Computer Architecture HW #5” in the subject line of your email.
Turn in the rest of the homework (problem 2 and 3) to the TA at office 211.
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