得在這兩天生出程式碼來
figure我會傳給你們
cherubchao@msn.com
辛苦的phylin被我煩了好幾天
實在不好意思再打擾他了...
各位強者有請了orz
用verilog語法
Design a binary counter with parallel load, as shown in Figure 5-12.
Note :
1. a clock cycle is 10 time units. clock = 0 at time 0.
2. Since the counter does not has reset signal, you have to load 4'b0000
into the counter at time 0 and set LOAD = 0, COUNT = 1 at time 10
to start the counter.
3. Simulation stops at time 1024.
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※ 編輯: chericherub 來自: 61.229.157.162 (07/04 00:50)