I am designing a prescaler (Multi Modulus Divider) to provide divide ratio
from 2 to 255 for 4GHz vco clock. Basically that is just a cascade of 7
cml_divide_by_2/3_cell.
Does anyone know what test cases should I run to verify the prescaler design
in detail? Like which divide ratio(s) can stress the circuit most? How to
check if prescaler works under dithering scenario?
Thanks and happy holiday
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