[心得] verilog

[DecadentX (失蹤很久的鑰匙)]

寫 code 的一些心得分享
如果有 更好的 coding style 請不吝指正
其實我是想賺好文 XD

-------------------------------------------------------
counter 的寫法

reg [4:0] counter;       //會變成 FF or register
wire [4:0] counter_next; //訊號線

always @(posedge clk or negedge reset)
if(~reset)
counter <= 5'b0;
else
counter <= counter_next;

assign counter_next = (enable) ? counter + 1'b1 : 0 ;
這樣可以很清楚的將 edge triage (sequental circuit)
和 level triage (combinational circuit) 分開

會比下面寫法好
always@(posedge clk or negedge rst)
if(~rst)
   counter <= 5'b0;
else
   counter <= counter + 1'b1;

-----------------------------------------------------------
而Final State Machine寫法也是
把 sequential 和 combinational 分開寫
* 表示會用到的變數

// Internal State REG
reg[StateSize-1:0] state;
reg[StateSize-1:0] next_state;
//FSM state assignment
//Sequental circuit
always @ (posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        state <= IDLE;
    end else begin
        state <= next_state;
    end
end

/////////////////////////////////////////////
//Combinational circuit

always @( * ) begin
    next_state = IDLE;
  case (state)
   IDLE: begin
        if( * ) begin
            next_state = A;
        end else begin
            next_state = B;
        end
    end
    A: begin
        if( * ) begin
           next_state = B;
       end else begin
            next_state =IDLE;
        end
    end
    B: begin
        if( * ) begin
           next_state = A;
       end else begin
            next_state =B;
        end
    end
    default : begin
        $display ("Moudle State : Error State !!");
    end
  endcase
end

--
※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 61.31.163.214
※ 編輯: DecadentX       來自: 61.31.163.214        (12/30 04:09)
推 paullai:推~
推 paullai:電板也非常歡迎此類文章  ^^/
推 paullai:也歡迎大家投稿～
推 pow:"Finite State Machine"
推 mouein:XD  樓上推才看到~~
推 Seals:厚 VHDL 地時代已經過去了嘛? :(
推 jcboy:兩個都會不就好了嗎:)？
→ DecadentX:最後狀態機~~~XD