作者ryeko (Cry for tomorrow)
看板Electronics
標題Re: [問題] verilog中的`timescale
時間Thu Mar 8 12:00:49 2007
※ 引述《kahang (終於大四了耶^^)》之銘言:
: 請問一下
: 我從書上看到它的用法是
: `timescale reference_time_unit/time_precision
: 可是還是不懂它的意思....||||
reference_time_unit: time unit of the Delay specification
time_precision: decimal place to round
: 可以告訴我reference_time_unit跟time_precision的關係跟例子嗎
: 謝謝
EX.
`timescale Unit/Precision Delay Time delay
__________________________________________________
`timescale 10ns/1ns #5 50ns
`timescale 10ns/1ns #5.738 57ns
`timescale 10ns/10ns #5.5 60ns
`timescale 10ns/100ps #5.738 57.4ns
--
※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 140.116.133.102
推 luckyBF:簡單明瞭~~酷 03/08 12:40
推 kahang:謝謝你:) 03/08 17:06