推 zeowo:標題錯誤 02/28 10:01
搜尋前文也有人問過，有人說資訊少給
有人說只要IC前後值即可算出speedup
但解答的其它指令(包括j,beg,bne指令)=3cycle=3ns
我還是不知道是從何而來的，我看後面算CPI也會用
到這個值。不知有無先進能了解這題為何解答如此呢？？
提供題目如下供先進們參考，謝謝
There is an unpipelined processor that has a 1 ns
closk cycle and that uses 4cycles for ALU
operations and 5 cycles for memory operations. Assume that the
relative frequencies of these operations are 40%,20% and 40%
respectively. Suppose that due to clock skew and setup, pipelining
the processor adds 0.2 ns of overhead to the clock. Ignoring any
latency impact, how much speedup in the instruction execution rate
will we gain from a pipeline implementation?
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