課程名稱︰交換電路與邏輯設計
課程性質︰系定必修
課程教師︰李君浩、李建模、盧奕璋、簡韶逸
開課學院：電資學院
開課系所︰電機工程學系
考試日期（年月日）︰2007.12.27
考試時限（分鐘）：50
是否需發放獎勵金：是，謝謝
（如未明確表示，則不予發放）
試題 :
1.[25 points] Please convert a S-R flip-flop to a J-K flip-flop by adding
external gates.
2.[25 points] Complete the timing diagram in Figure Q2(b) for the circuit in
Figure Q2(a). Note that the Ck inputs on the two flip-flops are different.
┌────────┐
│ ┌────┐ │ ┌────┐
│ ┌┴───┐│ │ ┌┴───┐│
│ │Q1' Q1││ │ │Q2' Q2││
│ │ ││ │ │ ││
Clear ─┘0│CLR ││ └ 0 ┤CLR ││
│ ││ │ ││
│Ck D1││ │Ck D2││
│△ ││ │△ ││
└───┬┘│ └┬──┬┘│
0 └─┘ │ └─┘
│ │
└─────────┘
┌─┐ ┌──────
Clear ──┘ └─┘
┌┐┌┐┌┐┌┐┌┐
Clock ┘└┘└┘└┘└┘└─
Q1
Q2
3. [25 points] Design a 3-bit counter which counts in the sequences
CBA=001,100,101,111,110,010,011,001,.....
With D flip-flops.
4. [25 points] A sequential circuit has one input(X) and one output(Z). Draw
a Mealy state graph (nine states are sufficient) for the following case:
The output is Z=1 iff the total number of 1's received is divisible by 3
and the total number of 0's received is an even number greater than zero.
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