課程名稱︰交換電路與邏輯設計
課程性質︰系訂必修
課程教師︰李君浩 簡韶逸 李建模 盧奕璋
開課學院：電資學院
開課系所︰電機系
考試日期（年月日）︰2008.12.25
考試時限（分鐘）：50分鐘
是否需發放獎勵金：是
試題 :
1.[10 points] Design a positive-triggered J-K flip-flop from S-R latches.
2.Solve the following problems.
(a)[20 points] Design a 3-bit counter which counts in the sequences CBA=000,
111,001,110,010,101,011,100,000,111... with T flip-flops.
(b)[10 points] Design a 3-bit counter, where two new input pins "count" and
"clear_n" are added. The function of this new counter is shown as
following table. (Hint: you don't have to re-design the counter. You can
design it by modifying the circuits in (a).)
clock count clear_n │ C+B+A+
───────────┼────────
x x 0 │ 000
↑ 0 1 │ CBA
↑ 1 1 │Normal operation
3.A Mealy circuit examines a string of 0's and 1's applied to the X-input and
generates an output Z=1 only when the input sequence, 1010, occurs. The
output Z=1 is coincident with the second 0 of the input sequence, 1010.
Example:
X = 0 1 0 1 1 1 0 1 0 1 0
Z = 0 0 0 0 0 0 0 0 1 0 1
(a)[20 points] Please provide the state graph of the circuit.
(b)[10 points] Please provide the state table of the circuit.
(c)[20 points] If D flip-flops are used, please provide the input maps and
input equations for the flip-flops; and the output map and output equation
for Z.
(d)[10 points] Please draw the circuit to implement this design.
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