課程名稱︰交換電路與邏輯設計
課程性質︰必修
課程教師︰簡韶逸
開課學院：電機資訊學院
開課系所︰電機工程學系
考試日期（年月日）︰103/12/18
考試時限（分鐘）：50分鐘
試題 :
Switching Circuits & Logic Design, Fall 2014
Quiz #2 (2:20pm~3:10pm, 2014/12/18)
Problem 1: (35 points)
A latch can be constructed from an OR gate and an AND gate, and an inverter
connected as follows:
http://ppt.cc/MDSa
(a) (10%) What restriction must be placed on R and H so that P will always
equal Q' (under steady-state conditions)?
(b) (15%) Fill the next-state table and derive the characteristic (next-state)
equation for the latch.
http://ppt.cc/5c8N
(c) (10%) Complete the following diagram for the latch.
http://ppt.cc/7LmA
Problem 2: (65 points)
For a sequential circuit with an input pin X, an output pin Z, and an active-
low asynchronous clear pin ClrN, the state transition table is shown as
follows. Please answer the followings questions.
http://ppt.cc/rjnM
(a) (5%) Is it a Moore machine or a Mealy machine?
(b) (10%) Please draw the state graph. Let S_0 = 000, S_1 = 001, S_2 = 010,
S_3 = 011, S4 = 100. +
(c) (10%) Please derive the next state (ex. A = f_A(X, A, B, C)) and output
equations.
(d) (10%) Design the sequential circuit where A, B, and C are all implemented
by positive-edge-triggered D flip-flops.
(e) (15%) Please finish the following timing diagram. Indicate the false output
if there is anyone. (draw the timing diagram on your answer sheet)
http://ppt.cc/HioB
(f) (15%) Design the same circuit but replace the combinational circuit part
with a ROM. Please show both the circuit and the content of the ROM.
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※ 編輯: NTUkobe (140.112.73.140), 12/20/2014 20:40:37