[試題] 101下 劉深淵 類比積體電路設計

[FAlin (FA（バルシェ應援）)]

課程名稱︰類比積體電路設計
課程性質︰系訂選修
課程教師︰劉深淵
開課學院：電資學院
開課系所︰電機系
考試日期（年月日）︰2013年5月7日
考試時限（分鐘）：180分鐘(2:20~5:20)
是否需發放獎勵金：是
（如未明確表示，則不予發放）

試題 :

1. Describe the basic five processing steps to fabricate the CMOS device. (10%)

2. (a) Explain the layout schemes how to realize two matched MOS devices with
       wide width. (5%)
   (b) Plot the layout of two matched capacitors with the ratio of 1:8.
　　   Explain your considerations. (5%)

3. (a) Please describe the equation of the threshold voltage for an NFET. (5%)
   (b) Calculate the zero-biased threshold voltage of an NFET at 27'C with the
       following parameters：the number of positively charge ions at the oxide
       silicom interface per area is Nss = 1*10^2 cm^-2 , NA = 3*10^16 cm^-3,
       gate doping ND = 4*10^19 cm^-3, tox = 200Å(埃), k = 1.38 * 10^-23 J/K,
       ni = 1.45*10^10 cm^-3,εox = 3.9*8.854*10^-14 F/cm,
       εsi = 11.7*8.854*10^-14 F/cm. (10%)

4. Neglect the body effect and channel length modulation. Please derive the
   zero of Fig.A1.(5%) (課本圖10.40(b))

5. (a) Derive the transfer function of Fig.A2. (10%) (課本圖10.38)
   (b) Assume its second pole is much larger than the first pole, please prove
       ωp1 ≒ 1/gm1*RL*Rs*Cc, and ωp2 ≒ gm2*Rs*gm1/CL. (5%)

6. Consider the channel length modulation effect to calculate the small-signal
   differential gain (5%) common-gain (5%) and CMRR (5%) for Fig.A3.
   (課本圖5.21)

7. Derive the maximum and minimum input common-mode ranges of Fig.A3. (10%)
   (課本圖5.21)

8. A current mirror is shown in Fig.A4.(課本圖5.14(a)) Assume M1, M2, M5 and M6
   have the same size. To minimize the voltage headroom of the voltage X,
   please derive the design equation for Iout = I1. (10%)

9. Please describe the advantages and disadvantages between the folded-cascode
   opertional amplifier and telescopic one. (10%)

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