課程名稱︰計算機結構
課程性質︰必帶
課程教師︰洪士灝
開課學院：電機資訊學院
開課系所︰資訊工程學系
考試日期（年月日）︰2012/11/8
考試時限（分鐘）：120
是否需發放獎勵金：是
（如未明確表示，則不予發放）
試題 :
Computer Architecture
Midterm Exam
Fall 2012
1.(10%) If you want your program to go fast, among Perl, C, and Java, which
would you use to write your program? What are the main differences between
these three languages?
2.(40%)For the MIPS instruction set architecture:
(a) (10%) What are the instruction formats? Please explain each instruction
format and list the MIPS instructions used by instrction format.
(b) (10%) What are the addressing modes? Please explain each addressing
mode and use MIPS instructions as examples to illustrate the use of each
address mode.
(c) (10%) What are the hazards that can occur in a pipelined datapath?
Please list the types of hazards and illustrate each type of hazard with
examples.
(d) (10%) In a pipelined datapath, what types of hazards can be eliminated
by "forwarding" or "bypassing"? How would the control detect the hazards
that can be eliminated? How to implement "forwarding" in the pipelined
datapath?
3.(20%) A 10-stage instruction pipeline runs at a clock rate of 1GHz. The
data forwarding scheme and the instruction mix are such that for 15% of
instructions one bubble, for 10% two bubbles, and for 5% four bubbles must
be inserted in the pipeline. The equivalent single-cycle implementation would
lead to a clock rate of 150MHz.
(a) (10%) What is the reduction in pipeline throughput over the ideal pipeline
as a result of bubbles?
(b) (10%) What is the speedup of the pipelined implementation over the single-
cycle implementation?
4.(20%) A program consists of two nested loops, with a single branch
instruction at the end of each loop and no other branch instruction anywhere.
The outer loop is executed 10 times and the inner loop 20 times. Determine
the accuracy of the following three branch prediction strategies:
(a)always predict taken,
(b)use 1 bit of history,
(c)use 2 bits of history.
Please draw a state diagram for the branch predictor with 2 bits of history.
5.(10%) In the context of computer architecture, what is "Power Wall"? How
has Power Wall impacted the trend of processor architecture? Comparing ARM
and x86, which architecture has better chance against the Power Wall? Why?
6.(Bonus, up to 10%) Could you propose a problem for this midterm exam and
provide a solution? To think of a problem is not easy, because you have to
understand the problem first. Please do not waste your time and my time
if you do not have a great new idea. We are looking for innovative, inspiring
, interesting problems.
7.(Bonus) Answering the question in this section will NOT add scores to this
exam, but impressive answers may increase your score in the "Class
Participation and Interactions" category. Please read the following news
article first.
聯發科砸30億 攻高階處理器 [經濟日報/記者謝佳雯/臺北報導]
2012.10.21 04:50 am
市場傳出，耕耘低價智慧手機有成的IC設計龍頭聯發科，計劃投資至少二、三十億元
投入發展中高階的應用處理器，並與宏達電、華碩、宏碁等品牌取得合作默契，共
同投入新產品開發與測試。
智慧型手機和平板電腦等移動裝置市場備受看好，聯發科的手機晶片不僅順利搶進大陸
和新興國家的低價智慧型手機市場，今年在中國市占率可望超過五成，亦相繼獲得中國
大陸白牌平板電腦和移動裝置採用。聯發科上周五股價上漲3.5元，以323.5元作收，三
大法人上周合計買超2277張。
雖然聯發科在新興市場成果豐碩，但遲遲未獲國際一線品牌採用，在政府有意打造國內
智慧手持裝置供應鏈的引導下，居手機、平板電腦「大腦」地位的處理器，為關鍵零組
件自製的重點。
市場傳出，聯發科已向經濟部提出中高階處理器(AP)開發計畫，已組成百人團隊打造高
階產品，投資規模至少二、三十億元，並以全球手機龍頭高通(Qualcomm)現行高階處理
器S4系列為開發指標。
為使新產品有出海口，聯發科也找下游廠合作，除了華碩、宏碁外，市場傳出，聯發科
已和宏達電取得合作共識，目前已開始和國內三大品牌廠著手討論新產品的開發規格、
時程等，未來產品下單對象可望為高階製程布局完整的臺積電。
雖然開發一顆新的應用處理器必須涵蓋通訊、繪圖、浮點運算等不同領域，開發時程往
往需要3年的時間，但聯發科已加快腳步，努力壓縮時間。業界預估，聯發科有機會在
明年底完成樣品，後年開始與合作的系統廠展開樣品測試並商品化。
(a) According to the article, what are the products that MediaTek(聯發科) is
best known for? Why does MediaTek suddenly want to change their strategies?
(b) How has HTC, Asus, and Acer been doing recently? Why didn't they use
MediaTek's chips before? Why are they suddenly interested in MediaTek's
chips now?
(c) What kind of talents will MediaTek try to recruit? What kind of skills
and courses are related to the development of advanced application processors?
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