[試題] 98下 顧孟愷 數位電子學 期末考

[oscarchichun (ㄍ一)]

課程名稱︰數位電子學
課程性質︰系必修
課程教師︰顧孟愷
開課學院：電資學院
開課系所︰資工系
考試日期（年月日）︰2010/6/21
考試時限（分鐘）：180
是否需發放獎勵金：是
（如未明確表示，則不予發放）

試題 :

Digital Electronics Final

        Instructor:Mong-Kai Ku
                6/21/2010
Grading: Total 100 points

1.
(a)(8%) Draw the full wave bridge rectifier circuit.
(b)(8%) When vs>0, explain the circuit operation; which diode turns off and
   which diode turns on.

2.MOSFET
(a)(5%) Explain why NMOS transistor is faster than PMOS?
(b)(10%) Use covalent bond model to explain why stretch silicon technique can
   improve MOS transistor performance.

3.(9%) Draw circuit symbols.
(a) Inductor
(b) Zener diode
(c) Three terminal PMOS transistor

4.(20%) Find the Q-point for the transistor in the following figure for
  R1 = 10kΩ, R2 = 22kΩ, R3 = 2.4kΩ, R4 = 1.2kΩ and VDD = 12V.
  Assume that VTO = 1, γ = 0, W/L = 20/1

-------------------------------------------------
|                       |                       |
|                       |                       |
R2                      R4                      |
|                       |                       |
|                     ---                       +
|--------------------|←-----------------      VDD
|                     ---               |       |
|                       |               |       |
|                       |               |       |
R1                      R3              |       |
|                       |               |       |
|                       |               |       |
-------------------------------------------------

5.(20%)A high-performance microprocessor design requires 100 million logic
  gates and is placed in a package that can dissipate 100W.
  (a) What is the average power that can be dissipated by each logic gate on
      the chip?
  (b) If a supply voltage of 2.5V is used, how much crttent can be used by
      each gate?
  (c) If the average gate delay for these circuits must be 1ns, what is the
      power-delay product required for the circuits in this design?

6.(20%) From the layout, please draw the circuit diagram and write the Boolean
  equation for this logic gate.

                     VDD:       Y:        Ground:
Polysilicon gete        d  N    y       N       g
               ↓       dddN    y       N       g
               A:aaaaaaaaaaaaaaayaaaaaaaNaaaaaa g
                           N    y       N       g
                           N    y       N       g
                        nnnn    y       N       g
                        n  N    y       N       g
               B:bbbbbbbnbbbbbbbybbbbbbbbbbbbbb g
                        n  N    y       N       g
                        n  yyyyyy       N       g
                        n  N       nnnnnn       g
                        n  N       n    N       g
               C:cccccccnccccccccccnccccccccccc g
                        n  N       n    N       g
                        n  N       n    ggggggggg←Metal
                        n  N       n    N
               D:dddddddnddddddddddnddddddddddd
                        n  N       n    N
                        nnnn       nnnnnn
                           N            N
                           ↑p+         ↑n+      NMOS devices
PMOS devices

-------------------n-well---------


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※ 編輯: oscarchichun    來自: 140.112.30.88        (06/29 09:40)