課程名稱︰邏輯電路
課程性質︰工科海洋系光機電組、資組必修
課程教師︰黃乾綱
開課學院：工學院
開課系所︰工科海洋系
考試日期（年月日）︰2008.01.18
考試時限（分鐘）：9:30~12:10
是否需發放獎勵金：是
（如未明確表示，則不予發放）
試題 :
(Please DON'T provide your answers ONLY.)
1.(25%) (Combinational Circuit) A BCD-to-seven-segment decoder is a
combinational circuit that convarts a decimal digit in BCD (4-bit input
w, x, y, z) to an appropriate code for the selection of segments in a
indicator used to display the decimal digit in a familiar form. The
seven outputs of the decoder (a, b, c, d, e, f, g) select the
corresponding segments in the display as shown in Fig (a). The numeric
display chosen to represent the decimal digit is shown in Fig (b).
Using a truth table and Karnaugh maps, design the BCD-to-seven-segment
decoder.
(Hint:there are don't-care conditions.)
a
─ ─ ─ ─ ─ ─ ─ ─ ─
f|g |b | | |b | | | | | | | | | | |
─ ─ ─ ─ ─ ─ ─ ─
e|d |c | | |c | | | | | | | | | |
─ ─ ─ ─ ─ ─ ─
(a)Segment designation (b)Numerical designation for display
(a) (10%) Use an n-to-2^n-line decoder and OR gates to implement this
combinational circuit. Draw the circuit.
(b) (10%) Use multiplexer to implement a,b,c outputs of this combinational
circuit.
(c) (5%) Use ROM to inplement this combinational circuit. Decide the size of
ROM (number of words and number of bits per word) and derive the
ROM programming table.
2.(30%) (Synchronous sequential circuit) Reduce the number of state in the
following state to the minimum:
Next State Output
Present State x=0 x=1 x=0 x=1
a f b 0 0
b d c 0 0
c f e 0 0
d g a 1 0
e d c 0 0
f f b 1 1
g g h 0 1
h g a 1 0
(a) (10%) Tabulate the reduced table
(b) (5%) Draw the reduced state diagram
(c) (10%) Design the sequential circuit with D flip-flops
(State Table - 3%, flip-flop input function - 4%, Circuit - 3%)
(d) (5%) What kind of finite state machine is this sequential circuit,
Mealy model or Moore model?
3.(30%) (Synchronous sequential circuit) Design a counter with the following
repeated binary sequence: 0, 1, 2, 3, 4, 5, 6.
(a) (10%) Use JK flip-flops.
(State Table - 3%, flip-flop input function - 4%, Circuit - 3%)
(b) (10%) Use T flip-flops.
(State Table - 3%, flip-flop input function - 4%, Circuit - 3%)
(c) Use a 4-bit synchronous binary counter
i. (5%) Using an AND gate and the load input
ii. (5%) Using a NAND gate and the asynchronous clear input
4.(15%)(Asynchronous sequential circuit) Analysis the asynchronous sequential
circuit:
(a) (10%) Derive the transition table for the asychronous sequential
circuit show in the following figure.
(b) (5%) Determine the sequence of internal states Y1Y2 for the following
sequence of inputs x1x2:00, 10, 11, 01, 11, 10, 00.
x1──┬──NOT ───
│ NAND ──┐
│ ┌─ └─
│ │ NAND ─┐Y1
│ │ ┌─ │
x2─┬│─────┴ │ │
││ NAND ───┘ │
││ ┌ │
││ └───────────┘
│└───────
│ NAND─┐
│ ┌ └─
│ │ NAND─┐Y2
└──NOT ───────── │
│ │
└────────┘
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