課程名稱︰積體電路設計
課程性質︰選修
課程教師︰闕智達
開課學院：電機系
開課系所︰電資學院
考試日期（年月日）︰2008/1/18
考試時限（分鐘）：150
是否需發放獎勵金：是
試題 :
1.Explain or answer the following(5% each)
(a)Draw the schematic of H-tree clock distribution scheme.
(b)In structured design,there are four strategies,the first one is hierarchy,
what are the other three?
(c)Draw the block diagram of the 8-bit carry-select adder,partitioned into two
four-bit stages.
(d)Why reading DRAM cell is destructive?
(e)Draw the 6-T XOR gate circuit?
(f)Explain the advantage and disadvantage of NAND-type ROM and NOR-type ROM.
(g)Use the modified Baugh-Wooley method to multiply two four-bit two's
complement number:(-3)x5.
(h)Draw the circuit diagram of a sense amplifier based on different pair.
(i)Explain the function of the circuit in Fig.1. (schmitt trigger)
2.For the circuit in Fig.2 (課本 FIG 10.55 (b) )
(a)Give its name(3%)
(b)Draw the waveforms of clk,Q0,Q1,Q2,Q3 for 17 clock cycles.Assume very
small rise time and fall time.(5%)
(c)Explain the disadvantage of this circuit.(5%)
3.(a)Design a circuit that computes the signal "AgreaterthanB",which is "1"
when A>B and "0" otherwise. A,B are both 4-bit 2's complement numbers.
Let A be A3A2A1A0,and B be B3B2B1B0 with A3 and B3 being the MSBs.(8%)
(b)Write a verilog module for the circuit in (a).Note that you can only use
the following typical standard cells: FA,AND,OR,XOR,etc.(8%)
4.We have shown in class that circuit in Fig3 can implement "shift register".
Note that the SRAM used is a dual-port SRAM.It is usually more economic to
use single-port SRAM.
Design a shift register withthe same function as the circuit in Fig.3 and
use only single-port SRAM. You must draw its circuit diagram using SRAM and
typical standard cells.(15%)
Note: A single port SRAM can either read a word or write a word in one clock
cycle. (課本Fig 11.43(b))
5. In class we have talk about booth encoding by examining 3 bit at a time
(radix 4).Based on the radix-4 booth encoding table, draw the encoding table
for radix-8 booth encoding. In other words, now you need to consider 4-bits
at a time.Let the current be X3i,the previous bit (less significant bit) be
X(3i-1),and the next two bits be X(3i+1),X(3i+2).The encoding table has 16
cases.Tell in each case what operation need be performed.Note there is no
need to define several variables as in the radix-4 table (e.g, "X","2X","M")
(16%)
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※ 編輯: overflow2 來自: 140.112.174.136 (01/20 02:47)