課程名稱︰計算機結構與組合語言
課程性質︰資工系必修
課程教師︰莊永裕
開課學院：電資學院
開課系所︰資工系
考試日期（年月日）︰2007.11.12
考試時限（分鐘）：二個小時半
是否需發放獎勵金：是
（如未明確表示，則不予發放）
試題 :
●use * to represent the irrelevant values and the values not specified in the question.
●Please use the following notations for logic gates. Feel free to change the orientations of the gates and the positions of inputs and outputs. You are free to use other circuits. Howeve, if they are not introduced in the class, you have tio implement them before using them.
圖：NOT gate、AND gate、OR gate、4-bit 2-multiplexer、4-bit full adder、4-bit right shifter(省略不畫)
hlt add rd,rs,rt sub rd,rs,rt and rd,rs,rt xor rd,rs,rt shl rd,rs,rt shr rd,rs,rt lda rd,addr
ld rd,addr st rd,addr ldi rd,rt sti rd,rt bz rd,addr bp rd,addr jr rd jl rd,addr
1.(6%) What are the 8-bit 2's complement representations of the following decimal numbers? Please give both their binary and hexadecimal representations.
a.-10
b.-97
2.(8%)Implement a circuit to realize the 3-bit mod3 function. The circuit has a 3-bit input X=X2X1X0 and a 2-bit output Y=Y1Y0 satisfying Y=X%3. For example, if X is 101, then Y is 10 because 5$3=2.Write down the truth table and its corresponding logic expressions for Y1 and Y0.
3.(18%)In the class, we have implemented the 4-bit right-shifter. Note that, to beconsistent with the lecture, let Z0 and X0 represent the MSBs.
(a) Modify the right-shifter so that it implements sign extension. Write down the corresponding logic expressions for Z0, Z1,Z2 and Z3.
(b) Please implement a 4-bit left-shifter whose diagram is shown as Figure 1(a). It has two 4-bit inputs, X=X0X1X2X2 and S=S0S1S2S2, and a 4-bit output Z. Note that only one of Si will be on at a time and Z=X<<i when Si =1. Write down the logic expression for Zi.
(c) Use your 4-bit left-shifter and any circuits defined in the class to implement a 4-bit left/right-shifter(Figure 1(b))/ Tje corciot jas a 4-bit input X, a 1-bit input d and a 2-bit input S, where d specifies the shift direction. When d\1, the shift is to the left. Please draw the circuit. (No need to optimize.)
圖：Figure1(a)4-bit left shifter (b)4-bit left/right shifter(省略不畫)
4.(8%)Please explain why we need copy input 2 in TOY ALU. Hint: give the instructions which need it.
5.(8%)Why did we change the definition of jr from PC←R[d] to PC←R[t]?
6.(10%)Draw the required datapath on the accompanying answer sheet (Figure 4 and 5) for
(a)instruction fetch
(b)the set of ALU instructions(opcode1-6) and lda. Please only draw the necessary part but not the whole TOY datapath. Add multiplexers if necessary.
7.(10%) According to the TOY architecture(Figure 2), write down the logic expression for MUXmem and MUXregw in terms of inputs to control(clock, execute, fetch, cond_pos, cond_zero and 16 instrutions(hlt, add, sub, ...))
8.(12%) Refer to the TOY archtecture (Figure 2), please specify the operations of MUXpc, MUXmem, MUXregr, MUXalu, MUXregw, WRITEreg, WRITEmem and ALU_OP during the executeion stage for the instructions "xor", "store" and "load indirect". For example, the answer for "jump and link" would be MUXpc=0, MUXmem=*, MUXalu=1, MUXregw=01, WRITEreg=1, WRITEmem=0, ALU_OP=*.
9.(12%) Please trace the content of RA, RB and RC along time for the following TOY assembly program. And, what is the final output to stdout?
lda RA, 12
lda RB, 8
repeat sub RC, RA, RB
bz RC, exit
bp RC, positive
sub RB, RB, RA
bz R0, repeat
positive sub RA, RA, RB
bz R0, repeat
exit st RA, 0xFF
10.(8%) Assume that we have three TOY object codes A.obj, B.obj and C.obj. Their sizes are 18, 32 and 23 words for A, B and C respectively. Assume that program B.obj exports the symbol proc_b and its address is 0x10 in B.obj. Similarly, program C.obj exports the symbol var_c whose address is 0x0A in C.obj. Assume that the source code for A.obj includes the following two instrucions:
lda RA, var_c
jl RF, proc_b
After linking using "toylink A.obj B.obj C.obj>A.toy", what are the corresopnding machine code for the above two statements in the resulter TOY executable code?
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※ 編輯: sam9595 來自: 61.230.39.13 (11/13 00:12)