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課程名稱：自動機與形式語言
課程性質︰必修
課程教師︰甘宗左(雙班)、歐陽明(單班) 統一命題、考試
開課學院：電機資訊學院
開課系所︰資訊系
考試日期（年月日）︰2010/11/24
考試時限（分鐘）：180分鐘
是否需發放獎勵金：是
（如未明確表示，則不予發放）
試題 :
1. Prove the identity of each of the following Boolean equations, using
algebraic manipulation: (15%)
(a) (x+y)(x'+y) = y
(b) x+y(x+z)+xz = x+yz
(c) (xy+z'(s+t'))' = x'+y'+z+s't
編按：(c)小題有誤，單班將右式更正為：(x'+y')(z+s't)
雙班則為「若錯誤，請說明其錯誤」
2. (20%) Consider a sequential circuit shown in following diagram. It has one
input x, one output z with a clock trigger signal clk.
Please draw the output waveform of z.
電路圖：
http://img535.imageshack.us/img535/2249/dsc06428y.jpg
編按：雙班補充：JK FF之Q初始狀態為0；單班未說明。
Reference: JK FF & D FF
http://img24.imageshack.us/img24/9717/65790822.png
http://img830.imageshack.us/img830/7716/28718620.png
3. (25%)
(a) Please use NAND gates to implement AND, OR, NOT and XOR. (6%)
(b) The full adder has three inputs─A, B, and CI (carry-in)─and two outputs
─S (sum) and CO (carry-out). Please use NAND gates to implement the
full adder. (6%)
(c) Please design a 4-bit adder using the result of (a) and (b). (5%)
(d) Please redesign (c) above, and become a carry-look-ahead 4-bit adder.(8%)
編按：(a)、(b)小題僅能使用NAND閘；(c)、(d)小題可用已造好component
4. (10%)
Please refer to the following block diagram and implement the memoty cell by
using a D-Latch as core. Note that, the chip is active only when the "Chip
Enable" signal is going low.
圖：
http://img808.imageshack.us/img808/6863/memorycell.jpg
5. (20%) Please implement a four-bit Binary Multiplication circuit with 2
indicators. Note A_3 A_2 A_1 A_0 & B_3 B_2 B_1 B_0 is the input and C_6 C_5
C_4 C_3 C_2 C_1 C_0 is the output, where O_1 = high is overflow flag indecating
when the result of A ×B cannot be represented by C. O_2 = high is the zero
flag indicating when the result of A ×B is zero.
編按：可使用之前題目中造好之component
6. (10%) Please use the Quine-McCluskey method to simplify the following Boolean
function.
f(A,B,C,D) = Σ(6,8,9,10,11,12,13,14)
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