[問題] 關於prescaler design

[gggould (evanescent)]

※ [本文轉錄自 comm_and_RF 看板 #1D72ODr1 ]

作者: gggould (evanescent) 看板: comm_and_RF
標題: [問題] 關於prescaler design
時間: Thu Dec 30 14:26:19 2010

I am designing a prescaler (Multi Modulus Divider) to provide divide ratio
from 2 to 255 for 4GHz vco clock. Basically that is just a cascade of 7
cml_divide_by_2/3_cell.

Does anyone know what test cases should I run to verify the prescaler design
in detail? Like which divide ratio(s) can stress the circuit most? How to
check if prescaler works under dithering scenario?

Thanks and happy holiday

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推 obov:寫個script測全部
→ gggould:謝謝 那請問該如何測dither部分 例如要DIVIDE RATIO改變時
→ gggould:該apply control signal @ rising or falling clock edge