[請益] Verilog module reset寫法 2

[nc23nick (弄牛連)]

延續之前小弟在版上發問的問題，how to reset counter in state of FSM ?
小弟在top module 裡新增一條訊號線clear來reset state裡的counter
現在問題來了modelsim output waveform一切正常，但用ise燒fpga
吐出的波形在第一次clear觸發後訊號就都錯出(疑是control沒有被reset)
想請問大大小弟下面的寫法是否有誤?

top.m
===================================================================

always @(posedge clk or negedge rst) begin     // reset control of unit
        if (~rst) begin
                clear <= 0;

        end
        else if (curr_state == S4 && counter == 10'd127 ||
                 curr_state == S5 && counter == 10'd236 || ) begin
                clear <= 1;

        end
        else begin
                clear <= 0;

        end
end

===================================================================

state4.m
===================================================================

always @(posedge clk or negedge rst) begin
        if(~rst) begin
                control= 1;
                set = 0;
        end
        else begin
                if(set == 0) begin
                        control = 0;
                        set = 1;
                end
                else
                        control = (clear == 1) ? 0 : control + 1;
        end
end

===================================================================

--
※ 發信站: 批踢踢實業坊(ptt.cc), 來自: 36.232.134.192
※ 文章網址: https://www.ptt.cc/bbs/Electronics/M.1480751108.A.9CA.html
※ 編輯: nc23nick (36.232.134.192), 12/03/2016 15:46:50
→ r901042004: 多加一個state專門用來把counter歸零應該比較簡單，你
→ r901042004: 的counter次數這麼多應該不差一個clk吧？