Job Description
1 IC封裝的基板設計及佈局
1.1 IC封裝型式涵蓋覆晶封裝及打線型封裝，單晶片封裝及多晶片封裝
1.2 基板層數涵蓋2層至20層以上。有4層 (1-2-1) 板以上設計經驗為佳
1.3 最佳化高速訊號 (DDR, SerDes, PCIe...) 的線路佈局
1.4 非常了解基板設計規範及封裝製程規範
2 協同IC及印刷電路板的設計
2.1 提供 bump/ball 的配置建議給 IC/PCB 設計工程師以最佳化 Chip-Package-PCB
的設計
3 其他
3.1 專案管理
3.2 營運管理協助
Requirements
1 正直樂觀、主動積極、認真負責
2 具三年以上IC封裝基板佈局設計相關工作經驗
3 具有 Cadence APD 實際操作經驗
4 具大學以上學位且有修習過科學或工程相關課程者為佳.
資深工程師者不受此限
Company Offers
1 具市場競爭力的薪資及營運績效獎金
2 暢通的升遷管道以及不受限的職涯發展
3 年度旅遊補助津貼
上班時間: 星期一至星期五. 8:30AM - 17:30PM， 15分鐘上下班彈性時間
上班地點: 台北景美
月薪: NTD50K - NTD100K
履歷請直接寄至: julia.lin@sarcina-tech.com
公司網站: sarcinatech.com
Job Description
1 IC package substrate design and layout
1.1 Package type includes flip-chip and wirebond. Single die design and
multi-die design
1.2 Substrate layer count from 2 layers to 20+ layers. Preferred experience
is at least 4 layers (1-2-1)
1.3"High-speed (DDR, SerDes, PCIe...) signal routing optimization"
1.4 Good knowledge in substrate layout design rules and package assembly
design rules
2 Chip-Package-PCB co-design
2.1 Review die bump assignment and BGA ball assignment to provide suggestions
to optimize the design
3 Other assignments and tasks
3.1 Project management
3.2 Operation assistance
Requirements
1 "Enthusiastic, proactive, and responsible. Has integrity"
2 At least 3-year working experience on IC package substrate layout
3 Hands-on experience using Cadence Allegro Package Designer (APD)
4 A bachelor degree or above in science or engineering is preferred.
Outstanding candidate without a college degree will be considered
Company Offers
1 Competitive salary and bonus
2 Unlimited career growth opportunity in company
3 Annual vacation allowance
Working Hours: Monday - Friday. 8:30AM - 17:30PM with 15 minutes flexibility
Working Location: Jingmei, Taipei"
Monthly salary: NTD50K - NTD100K
Please send your resume directly to: julia.lin@sarcina-tech.com
Company website: sarcinatech.com
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